1. Field
The present disclosure generally relates to an integrated circuit with an adjustable clock frequency. More specifically, the present disclosure relates to an integrated circuit that includes an asymmetric frequency-locked loop (AFLL), which includes digitally controlled oscillators (DCOs), and which adjusts a clock frequency of a critical path based on variations in a power-supply voltage of the DCOs and the critical path.
2. Related Art
The operating frequency of an integrated circuit is typically specified at the lowest acceptable power-supply voltage (Vlow) for a critical path in the integrated circuit, i.e., the power-supply voltage for which the critical path has a non-zero timing margin. In addition, the power dissipation or power consumption of the integrated circuit is usually specified at the average power-supply voltage (Vnominal).
In general, clock-generating circuits on integrated circuits are designed to be stable and not to track variations in the power-supply voltage, such as changes associated with power-supply noise. Thus, ideally there is a fixed difference between Vnominal and Vlow during operation of the integrated circuit.
However, in practice the power-supply voltage usually decreases when there is an increase in the power consumption of the integrated circuit. In particular, when there is a transient increase in the power-supply current, the inductance (L) through a chip package of the integrated circuit can result in a voltage loss
      (          L      ⁢                        ⅆ          i                          ⅆ          t                      )    .This voltage loss can result in a failure on the critical path because of an insufficient timing margin caused by the drooped voltage.
In addition, the combination of the inductance L and on-chip capacitances can produce a resonance frequency between 50-100 MHz that also produces oscillations in the power-supply voltage. This is shown in FIG. 1, which illustrates an electronic resonance associated with the chip package of an existing integrated circuit. Note that, if the power-supply voltage drops below Vlow, the critical path in this integrated circuit may fail because of an insufficient timing margin.
As critical dimensions in integrated circuits continue to decrease, the sensitivity of integrated circuits to these power-supply effects increases. Notably, smaller critical dimensions are typically associated with higher clock frequencies (and smaller clock periods), which increases power consumption and, thus, increases voltage droop. Furthermore, as the clock frequency increases, the resonance frequency associated with the chip package may fall within the operating bandwidth of the integrated circuit and, thus, of the power-supply distribution system. (However, note that the voltage variations associated with this resonance are typically at too high a frequency to be addressed by a voltage regulator module in the power-supply distribution system.) Collectively, these effects may require additional voltage margin to be added when designing the integrated circuit to ensure proper operation, which may be prohibitive in terms of the cost, complexity and time to market of the integrated circuit.
Hence, what is needed is an integrated circuit without the above-described problems.